PNX1502E Datasheet, PDF (811/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 29: Endian Mode
Two standard solutions are provided to interface the DTL to the PMAN MTL network
buses:
• The “PMAN Buffer” connects the 32-bit DTL interface to the MTL-Bus.
• The “packer Lego” and “DMA Buffering” map the 32-bit DTL interface to the 64-bit
MTL Memory Bus.
Note that the connection from the 32-bit DTL interface to the MTL Bus uses swapping
only if the 32-bit DTL interface is not address invariant.
The following subsections show how unit data of different lengths travels across the
three key interfaces: the 32-bit DTL interface, the DCS Network and the MTL Memory
Bus.
6.2 DMA Across a DTL Interface
Modules that interface to the DTL bus can deal with data on the bus in two ways:
• Data can be put on the bus in their natural form (without flipping them for endian
mode but indicating the size of the data with cmd_data_size). In this case, the
module is not aware of the SYS_ENDIAN bit in the system. The module follows
DTL data ordering rules.
• Modules can put the data on the bus in the address invariant mode (Note: This is
also the 8-bit mode). In this mode, the module uses the SYS_ENDIAN bit to flip
the data appropriately depending on the size of the data and the system endian
mode.
6.2.1 DTL Data Ordering Rules
Data is transferred across the DTL Interface by the following rules:
• The value of cmd_data_size indicates the width of the data item(s) as 8 *
2^{cmd_data_size} bits. For example, with 8-bit data, cmd_data_size is set to 0x0, for
16-bit data, cmd_data_size is 0x1, etc.
• In all cases, the data item (e.g. Byte) that corresponds to the lowest address is
transferred on the low order data bits of the DTL rd_data or wr_data
Modules dealing with 8, 16 or 32-bit units must place bytes on the DTL interface given
in Table 7. The Endian Swap Units then convert the data into true address invariant
views based on the cmd_data_size.
Table 5: DTL Interface Rules
Module
Item Unit
Size
System
Endian Mode DTL_D[31:24]
DTL_D[23:16]
DTL_D[15:8]
DTL_D[7:0]
8 bits
either
item #4 with
address a+3
item #3 with
address a+2
item #2 with
address a+1
item #1 with
address a
16 bits
either
item #2 with address a+2
item #1 with address a
bits 15..8
bits 7..0
bits 15..8
bits 7..0
32 bits
either
item with address a
bits 31..24
bits 23..16
bits 15..8
bits 7..0
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
29-811