PNX1502E Datasheet, PDF (192/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 5: The Clock Module
Table 11: CLOCK MODULE REGISTERS …Continued
Bit Symbol
Acces
s
Value
Description
5
Invert_qvcp_clock
R/W 0
Invert QVCP clock
0 : do not invert the clock
1: invert the clock only to the qvcp block and not to the pad.
4
qvcp_output_select
R/W 0
QVCP output select
0: Seperate output mode, The clock to the qvcp and to the pad
share the same source, but have seperate paths. This mode is also
the LCD only mode (see QVCP/LCD description). If the LCD only bit
is set then this bit cannot be set to a ‘1’ (feedback mode).
1: Feedback output mode, The clock is driven to the pad then is
feedback to the clock block. It then goes through gating logic to the
qvcp block.
3
qvcp_output_enable_n R/W 1
QVCP output enable
0: output, the clock is generated internally
1: input, the clock is provided by an external source. Note: during
and after reset the xtal clock is forced onto the qvcp clock. In order
to actually allow the input clock to go to the qvcp this register must
be written to. This also implies that writing qvcp_output_enable_n =
1 overrides a sel_clk_qvcp = 0.
2:1 sel_clk_qvcp
R/W 00
The following 3 settings are valid when qvcp_output_enable_n = 0.
00: clk_qvcp = 27 MHz xtal_clk (see qvcp_output_enable_n).
01: clk_qvcp = PLL1
10: clk_qvcp = PLL1
11: clk_qvcp = XIO_ACK
The following setting is valid when qvcp_output_enable_n = 1 (The
input mode).
01: clk_qvcp_out = VDO_CLK1
0
en_clk_qvcp
R/W 1
1: enable clk_qvcp
Offset 0x04,7204
CLK_QVCP_PIX_CTL
31:7 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
5:3 div_clk_qvcp_pix
R/W 001
000: clk_qvcp_pix_src = qvcp_clk_out clock divided by 1
001: clk_qvcp_pix_src = qvcp_clk_out clock divided by 2
010: clk_qvcp_pix_src = qvcp_clk_out clock divided by 3
011: clk_qvcp_pix_src = qvcp_clk_out clock divided by 4
100: clk_qvcp_pix_src = qvcp_clk_out clock divided by 6
101: clk_qvcp_pix_src = qvcp_clk_out clock divided by 8
(refer to Figure 17 for the qvcp_clk_out)
2:1 sel_clk_qvcp_pix
R/W 00
00: clk_qvcp_pix = 27 MHz xtal_clk
01: clk_qvcp_pix = clk_qvcp_pix_src
10: clk_qvcp_pix = clk_qvcp_pix_src
11: clk_qvcp_pix = XIO_D[8]
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
5-192