PNX1502E Datasheet, PDF (629/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 20: 2D Drawing Engine
In 32-bit per pixel mode, all 256 bytes of each scanline of the PatRam are used. The
host must load the entire PatRam prior to initiating a BLT that uses a pattern. In this
mode, bytes 0..3 of the PatRam are the upper left pixel in the ram. Byte 0 is the LSB
of the pixel and contains the blue component, byte 1 contains the green component,
byte two contains the red component, and byte three is the alpha component (usually
unused).
The PatRam can be loaded in two different ways to load either color data or
monochrome data.
The 256 byte PatRamColor section of the register space allows direct byte/word/
DWORD access to the PatRam. This allows arbitrary pattern data to be loaded. 64
pixels of data must be loaded into the PatRam prior to use. This ranges from 64 to
256 bytes of data depending on color depth. Byte 0 of this space is the first byte of
PatRam scanline 0.
To assist in loading mono patterns, the 8 byte PatRamMono section of the register
space provides automatic color expansion of mono data while loading the PatRam.
Thus, the host only sends 16 bytes (four DWORDS) of data to initialize the entire
pattern regardless of color depth: MonPatFColor, MonoPatBColor, and 8 bytes of
mono data (64 bits). Each bit in the mono data stream loads the appropriate byte(s)
of the PatRam with either the foreground color if the bit is a 1, or else the background
color if the bit is a 0. Byte0/Bit7 loads the left pixel of scanline 0, byte1/Bit7 loads the
left pixel of scanline 1, etc.
4. Register Descriptions
The drawing engine uses five areas of memory space:
1. The first memory space area is for the drawing engine command registers. These
registers are used to set up and execute drawing engine commands. There is a
block of unused memory space that has been reserved for future drawing engine
functions.
2. The next area decoded is for monochrome pattern data. Although only 8 bytes of
monochrome pattern data are required, a 256-byte decode is implemented to
allow color expansion to occur to different areas of the pattern RAM.
3. The third decoded area is for full color pattern data. 64, 128, or 256 bytes of data
may be written to the pattern RAM.
4. The fourth area decoded is for “real time” drawing registers. Unlike command
registers which are pipelined, real time registers can be accessed immediately.
5. The last memory area decoded is a 64-KB area that is used to transfer host data
to the drawing engine.
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
20-629