PNX1502E Datasheet, PDF (125/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 3: System On Chip Resources
Section 7.1 details the VDI and VDO pin assignment based on the content of the
VDI_MODE and VDO_MODE MMIO registers. Section 9.1 and Section 9.2 on
page 2-99 give an overview of the different modes.
7.1 MMIO Registers for the Input/Output Video/Data Router
In the following tables
• The X associated with a bit value means ‘do not care’.
• (clk_vip FF) means the data is registered by the clock assigned to VIP before
presenting the signals to the VIP module.
• (clk_fgpi FF) means the data is registered by the clock assigned to FGPI before
presenting the signals to the FGPI module.
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
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