PNX1502E Datasheet, PDF (603/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 19: Memory Based Scaler
Table 8: Memory Based Scaler (MBS) Registers …Continued
Bit Symbol
Acces
s
Value
Description
31:29 VSP_PHASE_MODE[2: R/W 0
0]
Phase mode
0: 64 phases
1: 32 phases
2: 16 phases
3: 8 phases
4: 4 phases
5: 2 phases
6: fixed phase
7: linear phase interpolation (only valid for4 component mode)
28 Reserved
27:26 VSP_FIR_COMP[1:0] R/W
Vertical filter components
00: two components, 6 tap FIR each¹
01: reserved
10: three components, 4 tap FIR each
11: four components, 3 tap FIR each
1 _{Filter lengths differ when in de-interlacing mode.}
25:20 Reserved
19: 0 VSP_ZOOM_0[19:0]
R/W 0
Initial zoom for 1st pixel in line (unsigned, LSB = 2^-16)
2 0000 (hex): downscale 50%
1 0000 (hex): no scaling = 2 ⁰
0 8000 (hex): zoom 2 x
Offset 0x10 C244
Phase Control
31 Reserved
-
30:28 VSP_QSHIFT[2:0]
R/W 0
Quantization shift control
Used to change quantization before being multiplied with 0.5.
100 (bin): divide by 16
101 (bin): divide by 8
110 (bin): divide by 4
111 (bin): divide by 2
000 (bin): multiply by 1
001 (bin): multiply by 2
010 (bin): multiply by 4
011 (bin): multiply by 8
27:26 Reserved
-
25 VSP_QSIGN
R/W 0
Quantization sign bit
24:21 VSP_LDIFF_C[3:0]
R/W 0
Line offset for chroma line count (signed, needed for slicing only)
20 Reserved
-
19:14 VSP_OFFSET_C[12:8]
-
Initial start offset for chroma DTO
(Used for 4:2:0 scaling and de-interlacing only.)
13: 0 VSP_OFFSET_0[12:0] R/W 0
Initial start offset for DTO
Offset 0x10 C248
Initial Zoom delta
31:26 Reserved
25: 0 VSP_DZOOM_0[25:0] R/W 0
Initial zoom delta for 1 pixel in line (signed, LSB = 2^-27)
Used for non-constant scaling ratios.
Offset 0x10 C24C
Zoom delta change
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
19-603