PNX1502E Datasheet, PDF (761/828 Pages) NXP Semiconductors – Connected Media Processor

NXP Semiconductors
Volume 1 of 1
PNX15xx/952x Series
Chapter 25: I²C Interface
2.1.8 Data Shift Register
This register contains a byte of serial data to be transmitted or a byte which has just
been received. Like all the registers in this module, only bits 7-0 are used. Data in
DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7)
and, after a byte has been received, the first bit of received data is located at the MSB
(bit 7) of DAT. While data is being shifted out, data on the bus is simultaneously being
shifted in; DAT always contains the last byte present on the bus. Thus, in the event of
lost arbitration, the transition from master transmitter to slave receiver is made with
the correct data in DAT.
2.1.9 Related Interrupts
The serial interrupt signal (iic_intrn) issues an interrupt when any one of the 26
possible IIC module states are entered. The only state that never causes an interrupt
is state 0xF8, which indicates that no relevant state information is available.
2.1.10 Modes of Operation
The IIC module hardware may operate in any of the following four modes:
• Master Transmitter
• Master Receiver
• Slave Receiver
• Slave Transmitter
As a master, the IIC module will generate all the serial clock pulses and the START
and STOP conditions. A transfer ends with a STOP condition or with a repeated
START condition. Since a repeated START condition is also the beginning of the next
serial transfer, the I²C bus will not be released.
Two types of data transfers are possible on the I²C bus:
• Data transfer from a master transmitter to a slave receiver. The first byte
transmitted by the master is the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after each received byte.
• Data transfer from a slave transmitter to a master receiver. The first byte (the
slave address) is transmitted by the master. The slave then returns an
acknowledge bit. Next follows the data bytes transmitted by the slave to the
master. The master returns an acknowledge bit after each received byte except
the last byte. At the end of the last received byte, a “not acknowledge” is returned.
In a given application, the IIC module may operate as a master and as a slave. In the
slave mode, the IIC module hardware looks for its own slave address and the general
call address. If one of these addresses is detected, an interrupt is requested. When
the micro controller wishes to become the bus master, the hardware waits until the
bus is free before the master mode is entered so that a possible slave action is not
interrupted. If bus arbitration is lost in the master mode, the IIC module switches to
the slave mode immediately and can detect its own slave address in the same serial
transfer.
PNX15XX_PNX952X_SER_N_4
Product data sheet
Rev. 4.0 — 03 December 2007
© NXP B.V. 2007. All rights reserved.
25-761