TDA8029 Datasheet, PDF (44/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
When everything is satisfactory (voltage supply, card present and no hardware problems),
the system controller may initiate an activation sequence of the card. Figure 12 shows the
activation sequence.
After leaving the UART reset mode, and then configuring the necessary parameters for
the UART, it may set the bit START in register PCR (t₀). The following sequence will take
place:
• The DC-to-DC converter is started (t₁)
• V_CC starts rising from 0 V to 5 V or 3 V with a controlled rise time of 0.17 V/µs
typically (t₂)
• I/O rises to V_CC (t₃), (Integrated 14 kΩ pull-up to V_CC)
• CLK is sent to the card and RST is enabled (t₄).
After a number of clock pulses that can be counted with the time-out counter, bit RSTIN
may be set by software, then pin RST rises to V_CC.
The sequencer is clocked by ¹â„₆₄f_int which leads to a time interval T of 25 µs typical. Thus
t₁ = 0 to ³â„₆₄T, t₂ = t₁ + ³â„₂T, t₃ = t₁ + ⁷⁄₂T, and t₄ = t₁ + 4T.
START
V_UP
V_CC
I/O
RSTIN
CLK
RST
t₀
t₂
t₁
Fig 12. Activation sequence
t₃ t₄ = t_act
ATR
fce684
8.17 Deactivation sequence
When the session is completed, the microcontroller resets bit START (t₁₀). The circuit then
executes an automatic deactivation sequence shown in Figure 13:
• Card reset (pin RST falls LOW) (t₁₁)
• Clock (pin CLK) is stopped LOW (t₁₂)
• Pin I/O falls to 0 V (t₁₃)
• V_CC falls to 0 V with typical 0.17 V/µs slew rate (t₁₄)
• The DC-to-DC converter is stopped and CLK, RST, V_CC and I/O become
low-impedance to GNDC (t₁₅).
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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