TDA8029 Datasheet, PDF (25/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
locations higher than 1FFh (i.e., 0200h to FFFFh) will be performed with the MOVX DPTR
instructions in the same way as in the standard 80C51, so with P0 and P2 as
data/address bus, and P3.6 and P3.7 as write and read timing signals.
When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51. MOVX @Ri will provide an 8-bit address multiplexed with data on port 0 and any
output port pins can be used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs
the high order eight address bits (the contents of DPH) while port 0 multiplexes the
low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will
generate either read or write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 byte RAM (lower and upper
RAM) internal data memory. The stack must not be located in the XRAM.
1FFh
512-BYTE
XRAM
BY
MOVX
00h
FFh
UPPER
128-BYTE
INTERNAL
RAM
80h
LOWER
128-BYTE
INTERNAL
RAM
00h
FFFFh
200h
EXTERNAL
DATA
MEMORY
FFh
SPECIAL
FUNCTION
REGISTERS
80h
00h
00h
mce651
Fig 9. Internal and external data memory address space with EXTRAM = 0
8.6.1 Auxiliary register (AUXR)
Table 32: AUXR - auxiliary register (address 8Eh) bit allocation
7
6
5
4
3
2
-
-
-
-
-
-
1
0
EXTRAM
AO
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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