TDA8029 Datasheet, PDF (21/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0
SM1
SM2
REN
TB8
RB8
TI
1
1
1
0
1
1
X
RI
SCON
(98h)
received address D0 to D7
programmed address
COMPARATOR
mdb817
UART modes 2 or 3 and SM2 = 1: there is an interrupt if REN = 1, RB8 = 1 and received address is equal to programmed
address.
When own address is received, reset SM2 to receive the data bytes. When all data bytes are received, set SM2 to wait for
the next address.
Fig 7. UART multiprocessor communication, automatic address recognition
8.4 Interrupt priority structure
The TDA8029 has a 6-source 4-level interrupt structure.
There are three SFRs associated with the 4-level interrupt: IE, IP and IPH. The Interrupt
Priority High (IPH) register implements the 4-level interrupt structure. The IPH is located
at SFR address B7h.
The function of the IPH is simple and when combined with the IP determines the priority of
each interrupt. The priority of each interrupt is determined as shown in Table 23.
Table 23: Priority bits
IPH bit n IP bit n
0
0
0
1
1
0
1
1
Interrupt priority level
level 0 (lowest priority)
level 1
level 2
level 3 (highest priority)
Table 24: Interrupt Table
Source
Polling priority
Request bits
X0
1
T0
2
X1
3
T1
4
SP
5
T2
6
[1] Level activated.
[2] Transition activated.
IE0
TF0
IE1
TF1
RI, TI
TF2, EXF2
Hardware clear
N ^[1], Y ^[2]
Y
N ^[1], Y ^[2]
Y
N
N
Vector address
(hex)
03
0B
13
1B
23
2B
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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