TDA8029 Datasheet, PDF (23/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
8.4.3 Interrupt priority high register (IPH)
Table 29: IPH - interrupt priority high register (address B7h) bit allocation
7
6
5
4
3
2
1
-
-
PT2H
PSH
PT1H
PX1H
PT0H
0
PX0H
Table 30: IPH - interrupt priority high register (address B7h) bit description
Each interrupt priority is assigned with a bit in register IP and a bit in register IPH, see Table 23.
Bit
Symbol
Description
7 and 6 -
Not implemented. Reserved for future use ^[1]
5
PT2H
Timer 2 interrupt priority.
4
PSH
Serial port interrupt prioritizes.
3
PT1H
Timer 1 interrupt priority.
2
PX1H
External interrupt 1 priority.
1
PT0H
Timer 0 interrupt priority.
0
PX0H
External interrupt 0 priority.
[1] Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be logic 0, and its active value will
be logic 1. The value read from a reserved bit is indeterminate.
8.5 Dual DPTR
The dual DPTR structure is a way by which the TDA8029 will specify the address of an
external data memory location. There are two 16-bit DPTR registers that address the
external memory, and a single bit called DPS (bit 0 of the AUXR1 register) that allows the
program code to switch between them.
The DPS bit should be saved by software when switching between DPTR0 and DPTR1.
The GF bit (bit 2 in register AUXR1) is a general purpose user-defined flag. Note that bit 2
is not writable and is always read as a logic 0. This allows the DPS bit to be quickly
toggled simply by executing an INC AUXR1 instruction without affecting the GF or LPEP
bits.
The instructions that refer to DPTR refer to the data pointer that is currently selected using
bit 0 of the AUXR1 register. The six instructions that use the DPTR are listed in Table 31
and an illustration is given in Figure 8.
Table 31: DPTR Instructions
Instruction
INC DPTR
MOV DPTR, #data 16
MOV A, @A + DPTR
MOVX A, @DPTR
MOVX @DPTR, A
JMP @A + DPTR
Comment
increments the data pointer by 1
loads the DPTR with a 16-bit constant
move code byte relative to DPTR to ACC
move external RAM (16-bit address) to ACC
move ACC to external RAM (16-bit address)
jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by specifying the low or high
byte in an instruction which accesses the SFRs.
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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