TDA8029 Datasheet, PDF (35/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
Table 56: USR - UART status register (address Eh) bit allocation
Bit
7
6
5
4
3
Symbol
TO3
TO2
TO1
EA
PE
Reset
0
0
0
0
0
Access
read
2
OVR
0
1
FER
0
0
TBE/RBF
0
Table 57: USR - UART status register (address Eh) bit description
Bit
Symbol
Description
7
TO3
Time-out counter 3. TO3 = 1 when counter 3 has reached its terminal count.
6
TO2
Time-out counter 2. TO2 = 1 when counter 2 has reached its terminal count.
5
TO1
Time-out counter 1. TO1 = 1 when counter 1 has reached its terminal count.
4
EA
Early Answer. EA = 1 if the first start-bit on the I/O pin during ATR has been detected
between the first 200 and n_max clock pulses with pin RST in LOW state (all activities on
the I/O during the first 200 clock pulses with pin RST LOW are not taken into account)
and before the first n_max clock pulses with pin RST in HIGH state. These two features are
re-initialized at each toggling of pin RST. n_max = 384 for TDA8029HL/C1; n_max = 368 for
TDA8029HL/C2.
3
PE
Parity error.
In protocol T = 0, bit PE = 1 if the UART has detected a number of received characters
with parity errors equal to the number written in bits PEC[2:0] or if a transmitted
character has been NAKed by the card a number of times equal to the value
programmed in bits PEC[2:0]. It is set at 10.5 ETU in the reception mode and at
11.5 ETU in the transmission mode. A character received with a parity error is not
stored in register FIFO in protocol T = 0; the card should repeat this character.
In protocol T = 1, a character with a parity error is stored in the FIFO and the parity
error counter is not active.
2
OVR
Overrun. OVR = 1 if the UART has received a new character whilst URR was full. In this
case, at least one character has been lost.
1
FER
Framing Error. FER = 1 when I/O was not in high-impedance state at 10.25 ETU after a
start-bit. It is reset when USR has been read.
0
TBE/RBF
Transmit Buffer Empty / Receive Buffer Full. TBE and RBF share the same bit within
register USR: when in transmission mode the relevant bit is TBE; when in reception
mode it is RBF.
TBE = 1 when the UART is in transmission mode and when the microcontroller may
write the next character to transmit in register UTR. It is reset when the microcontroller
has written data in the transmit register or when bit T/R in register UCR1 has been
reset either automatically or by software. After detection of a parity error in
transmission, it is necessary to wait 13.5 ETU before rewriting the character which has
been NAKed by the card (manual mode, see Table 55).
RBF = 1 when register FIFO is full. The microcontroller may read some of the
characters in register URR, which clears bit RBF.
8.10.3 Card registers
When working with a card, the following registers are used for programming some specific
parameters.
8.10.3.1 Programmable divider register (PDR)
This register is used for counting the card clock cycles forming the ETU. It is an
auto-reload 8 bits counter counting from the programmed value down to 0.
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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