TDA8029 Datasheet, PDF (18/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
Table 16: SCON - serial port control register (address 98h) bit description
Bit
Symbol
Description
7
SM0/FE
The function of this bit is determined by SMOD0, bit 6 of register
PCON. If SMOD0 is set then this bit functions as FE. This bit functions
as SM0 when SMOD0 is reset. When used as FE, this bit can only be
cleared by software.
SM0: Serial port mode bit 0. See Table 17.
FE: Framing Error bit. This bit is set by the receiver when an invalid
stop bit is detected; see Figure 6. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit in
register PCON must be set to enable access to FE.
6
SM1
Serial port mode bit 1. See Table 17
5
SM2
Serial port mode bit 2. Enables the automatic address recognition
feature in modes 2 or 3. If SM2 = 1, bit Rl will not be set unless the
received 9th data bit (RB8) is logic 1; indicating an address and the
received byte is a given or broadcast address. In mode 1, if SM2 = 1
then Rl will not be activated unless a valid stop bit was received, and
the received byte is a given or broadcast address. In mode 0, SM2
should be logic 0.
4
REN
Enables serial reception. Set by software to enable reception. Cleared
by software to disable reception.
3
TB8
The 9th data bit transmitted in modes 2 and 3. Set or cleared by
software as desired. In mode 0, TB8 is not used.
2
RB8
The 9th data bit received in modes 2 and 3. In mode 1, if SM2 = 0,
RB8 is the stop bit that was received. In mode 0, RB8 is not used.
1
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in
mode 0, or at the beginning of the stop bit in the other modes, in any
serial transmission. Must be cleared by software.
0
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in
mode 0, or halfway through the stop bit time in the other modes, in any
serial reception (except if SM2 = 1, as described for SM2). Must be
cleared by software.
Table 17: Enhanced UART Modes
SM0
SM1
MODE
0
0
0
0
1
1
1
0
2
1
1
3
DESCRIPTION
shift register
8-bit UART
9-bit UART
9-bit UART
BAUD-RATE
1_{⁄12fXTAL1}
variable
1_{⁄32 or} 1_{⁄64fXTAL1}
variable
8.3.2 Automatic address recognition
Automatic address recognition is a feature which allows the UART to recognize certain
addresses in the serial bit stream by using hardware to make the comparisons. This
feature saves a great deal of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This feature is enabled by
setting the SM2 bit in register SCON. In the 9-bit UART modes (modes 2 and 3), the
Receive Interrupt flag (RI) will be automatically set when the received byte contains either
the ‘given’ address or the ‘broadcast’ address. The 9-bit mode requires that the 9th
information bit is a logic 1 to indicate that the received information is an address and not
data. Figure 7 gives a summary.
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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