TDA8029 Datasheet, PDF (37/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
CLK
2 × CLK
MUX
CKU
Fig 10. ETU generation
÷ 31 OR 32
÷ PDR
fce872
ETU
Table 62: Baud rate selection using values F and D
Card clock frequency f_CLK = 3.58 MHz for PSC = 31 and f_CLK = 4.92 MHz for PSC = 32 (example: in this table; 12 means
prescaler set to 31 and PDR set to 12)
D
F
0
1
2
3
4
5
6
9
10
11
12
13
1
31;12 31;12 31;18 31;24 31;36 31;48 31;60 32;16 32;24 32;32 32;48 32;64
9600 9600 6400 4800 3200 2400 1920 9600 6400 4800 3200 2400
2
31;6 31;6 31;9 31;12 31;18 31;24 31;30 32;8 32;12 32;16 32;24 32;32
19200 19200 12800 9600 6400 4800 3840 19200 12800 9600 6400 4800
3
31;3 31;3 -
38400 38400
31;6 31;9 31;12 31;15 32;4 32;6 32;8 32;12 32;16
19200 12800 9600 7680 38400 25600 19200 12800 9600
4
-
-
-
31;3 -
31;6 -
32;2 32;3 32;4 32;6 32;8
38400
19200
76800 51300 38400 25600 19200
5
-
-
-
-
-
31;3 -
32;1 -
32;2 32;3 32;4
38400
153600
76800 51300 38400
6
-
-
-
-
-
-
-
-
-
32;1 -
32;2
153600
76800
8
31;1 31;1 -
115200 115200
31;2 31;3 31;4 31;5 -
57200 38400 28800 23040
32;2 -
76800
32;4 -
38400
9
-
-
-
-
-
-
31;3 -
-
-
-
-
38400
8.10.3.3 Guard time register (GTR)
The guard time register is used for storing the number of guard ETUs given by the card
during ATR. In transmission mode, the UART will wait this number of ETUs before
transmitting the character stored in register UTR.
Table 63: GTR - UART guard time register (address 5h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
GT7
GT6
GT5
GT4
GT3
GT2
GT1
GT0
Reset
0
0
0
0
0
0
0
0
Access
read and write
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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