TDA8029 Datasheet, PDF (28/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
8.10.1 General registers
8.10.1.1 Card select register (CSR)
This register is used for resetting the ISO UART.
Table 35: CSR - card select register (address 0h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
RIU
-
-
-
Reset
0
0
0
0
0
0
0
0
Access
read and write
Table 36: CSR - card select register (address 0h) bit description
Bit
Symbol
Description
7 to 4
-
Not used
1
RIU
Reset ISO UART. If RIU = 0, this bit resets a large part of the UART registers to their
initial value. Bit RIU must be reset to logic 0 for at least 10 ns duration before any
activation. Bit RIU must be set to logic 1 by software before any action on the UART can
take place.
2 to 0
-
Not used
8.10.1.2 Hardware status register (HSR)
This register gives the status of the chip after a hardware problem has been signalled or
when pin SDWN_N has been activated.
When PRTL1, PRL1, PTL or SDWN is logic 1, then pin INT0_N is LOW. The bits having
caused the interrupt are cleared when HSR is read (two f_int cycles after the rising edge of
signal RD).
In case of emergency deactivation by PRTL1, SUPL, PRL1 and PTL, bit START in the
power control register is automatically reset by hardware.
Table 37: HSR - hardware status register (address Fh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
SDWN
-
PRTL1
SUPL
-
PRL1
-
PTL
Reset
-
0
0
0
0
0
0
0
Access
read
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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