TDA8029 Datasheet, PDF (33/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
8.10.2.3 Mixed status register (MSR)
This register relates the status of the card presence contact PR1, the BGT counter, the
FIFO empty indication, the transmit/receive ready indicator TBE/RBF and the completion
of clock switching to or from ¹â„₂f_int.
Table 52: MSR - mixed status register (address Ch) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CLKSW
FE
BGT
-
-
PR1
-
TBE/RBF
Reset
-
1
0
-
-
-
-
-
Access
read
Table 53: MSR - mixed status register (address Ch) bit description
Bit
Symbol
Description
7
CLKSW
Clock Switch. CLKSW is set when the TDA8029 has performed a required clock switch
from ¹â„_nf_XTAL to ¹â„₂f_int and is reset when the TDA8029 has performed a required clock
switch from ¹â„₂f_int to ¹â„_nf_XTAL. The application shall wait this bit before entering
Power-down mode or restarting sending commands after leaving power-down (only
needed when the clock is not stopped during power-down). This bit is also reset by RIU
and at power-on. When the microcontroller wants to transmit a character to the card, it
writes the data in direct convention to this register.
6
FE
FIFO Empty. FE is set when the reception FIFO is empty. It is reset when at least one
character has been loaded in the FIFO.
5
BGT
Block Guard Time.
In T = 1 protocol, the bit BGT is linked with a 22 ETU counter, which is started at every
start-bit on pin I/O. If the count is finished before the next start-bit, BGT is set. This
helps checking that the card has not answered before 22 ETU after the last transmitted
character, or that the reader is not transmitting a character before 22 ETU after the last
received character.
In T = 0 protocol, the bit BGT is linked to a 16 ETU counter, which is started at every
start-bit on I/O. If the count is finished before the next start-bit, then the bit BGT is set.
This helps checking that the reader is not transmitting too early after the last received
character.
4 and 3
-
Not used.
2
PR1
Presence 1. PR1 = 1 when the card is present.
1
-
Not used.
0
TBE/RBF
Transmit Buffer Empty / Receive Buffer Full. This bit is set when:
• Changing from reception mode to transmission mode
• A character has been transmitted by the UART (except when a character has been
parity error free transmitted whilst LCT = 1)
• The reception buffer is full.
This bit is reset:
• After power-on
• When bit RIU in register CSR is reset
• When a character has been written in register UTR
• When the character has been read from register URR
• When changing from transmission mode to reception mode.
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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