TDA8029 Datasheet, PDF (22/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
8.4.1 Interrupt enable register (IE)
Table 25: IE - interrupt enable register (address A8h) bit allocation
7
6
5
4
3
2
1
0
EA
-
ET2
ES
ET1
EX1
ET0
EX0
Table 26: IE - interrupt enable register (address A8h) bit description ^[1]
Bit
Symbol
Description
7
EA
Global disable. If EA = 0, all interrupts are disabled; If EA = 1, each
interrupt can be individually enabled or disabled by setting or clearing
its enable bit.
6
-
Not implemented. Reserved for future use ^[2]
5
ET2
Timer 2 interrupt enable. ET2 = 1 enables the interrupt; ET2 = 0
disables the interrupt.
4
ES
Serial port interrupt enable. ES = 1 enables the interrupt; ES = 0
disables the interrupt.
3
ET1
Timer 1 interrupt enable. ET1 = 1 enables the interrupt; ET1 = 0
disables the interrupt.
2
EX1
External interrupt 1 enable. EX1 = 1 enables the interrupt; EX1 = 0
disables the interrupt.
1
ET0
Timer 0 interrupt enable. ET0 = 1 enables the interrupt; ET0 = 0
disables the interrupt.
0
EX0
External interrupt 0 enable. EX0 = 1 enables the interrupt; EX0 = 0
disables the interrupt.
[1] Details on interaction with the UART behavior in Power-down mode are described in Section 8.15.
[2] Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be logic 0, and its active value will
be logic 1. The value read from a reserved bit is indeterminate.
8.4.2 Interrupt priority register (IP)
Table 27: IP - interrupt priority register (address B8h) bit allocation
7
6
5
4
3
2
1
0
-
-
PT2
PS
PT1
PX1
PT0
PX0
Table 28: IP - interrupt priority register (address B8h) bit description
Each interrupt priority is assigned with a bit in register IP and a bit in register IPH, see Table 23.
Bit
Symbol
Description
7 and 6 -
Not implemented. Reserved for future use ^[1]
5
PT2
Timer 2 interrupt priority.
4
PS
Serial port interrupt priority.
3
PT1
Timer 1 interrupt priority.
2
PX1
External interrupt 1 priority.
1
PT0
Timer 0 interrupt priority.
0
PX0
External interrupt 0 priority.
[1] Do not write logic 1s to reserved bits. These bits may be used in future 80C51 family products to invoke
new features. In that case, the reset or inactive value of the new bit will be logic 0, and its active value will
be logic 1. The value read from a reserved bit is indeterminate.
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
22 of 59