TDA8029 Datasheet, PDF (12/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
8.2.1 Timer/counter 2 control register (T2CON)
Table 7:
7
TF2
T2CON - timer/counter 2 control register (address C8h) bit allocation
6
5
4
3
2
1
EXF2
RCLK
TCLK EXEN2
TR2
C/T2
0
CP/RL2
Table 8:
Bit
7
6
5
4
3
2
1
0
T2CON - timer/counter 2 control register (address C8h) bit description
Symbol
Description
TF2
Timer 2 overflow flag set by a timer 2 overflow and must be cleared by
software. TF2 will not be set when either RCLK or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by
a negative transition on T2EX and EXEN2 = 1. When timer 2 interrupt
is enabled, EXF2 = 1 will cause the CPU to vector to the timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not
cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
Receive clock flag. When set, causes the serial port to use timer 2
overflow pulses for its receive clock in modes 1 and 3. RCLK = 0
causes timer 1 overflows to be used for the receive clock.
TCLK
Transmit clock flag. When set, causes the serial port to use timer 2
overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0
causes timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to
occur as a result of a negative transition on T2EX if timer 2 is not being
used to clock the serial port. EXEN2 = 0 causes timer 2 to ignore
events at T2EX.
TR2
Start/stop control for timer 2. TR2 = 1 starts the timer.
C/T2
Counter or timer select timer 2.
0 = internal timer ⁽¹â„₁₂f_XTAL1)
1 = external event counter (falling edge triggered).
CP/RL2
Capture or reload flag. When set, captures will occur on negative
transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will
occur either with timer 2 overflows or negative transitions at T2EX
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on timer 2 overflow.
Table 9: Timer 2 operating modes
Mode
RCLK and TCLK
CP/RL2
TR2
16-bit auto-reload
0
0
1
Baud-rate generator
1
X
1
Off
X
X
0
8.2.2 Timer/counter 2 mode control register (T2MOD)
Table 10: T2MOD - timer/counter 2 mode control register (address C9h) bit allocation
7
6
5
4
3
2
1
0
-
-
-
-
-
-
T2OE
DCEN
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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