TDA8029 Datasheet, PDF (32/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
8.10.2 ISO UART registers
8.10.2.1 UART transmit register (UTR)
Table 48: UTR - UART transmit register (address Dh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
UT7
UT6
UT5
UT4
UT3
UT2
UT1
UT0
Reset
0
0
0
0
0
0
0
0
Access
write
Table 49: UTR - UART transmit register (address Dh) bit description
Bit
Symbol
Description
7 to 0
UT[7:0]
UART transmit bits. When the microcontroller wants to transmit a character to the card, it
writes the data in direct convention in this register. The transmission:
• Starts at the end of writing (on the rising edge of signal WR) if the previous character
has been transmitted and if the extra guard time has expired
• Starts at the end of the extra guard time if this one has not expired
• Does not start if the transmission of the previous character is not completed
• With a synchronous card (bit SAN within register UCR2 is set), only UT0 is relevant
and is copied on pin I/O of the card.
8.10.2.2 UART receive register (URR)
Table 50: URR - UART receive register (address Dh) bit allocation
Bit
7
6
5
4
3
Symbol
UR7
UR6
UR5
UR4
UR3
Reset
0
0
0
0
0
Access
read
2
UR2
0
1
UR1
0
0
UR0
0
Table 51: URR - UART receive register (address Dh) bit description
Bit
Symbol
Description
7 to 0
UR[7:0]
UART receive bits. When the microcontroller wants to read data from the card, it reads it
from this register in direct convention:
• With a synchronous card, only UR0 is relevant and is a copy of the state of the
selected card I/O
• When needed, this register may be tied to a FIFO whose length ‘n’ is programmable
between 1 and 8; if n > 1, then no interrupt is given until the FIFO is full and the
controller may empty the FIFO when required
• With a parity error:
– In protocol T = 0, the received byte is not stored in the FIFO and the error
counter is incremented. The error counter is programmable between 1 and 8.
When the programmed number is reached, then bit PE is set in the status
register USR and INT0_N falls LOW. The error counter must be reprogrammed to
the desired value after its count has been reached
– In protocol T = 1, the character is loaded in the FIFO and the bit PE is set to the
programmed value in the parity error counter.
• When the FIFO is full, then bit RBF in the status register USR is set. This bit is reset
when at least one character has been read from URR
• When the FIFO is empty, then bit FE is set in the status register USR as long as no
character has been received.
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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