TDA8029 Datasheet, PDF (39/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
Table 67: CCR - Clock configuration register (address 1h) bit allocation
Bit
7
6
5
4
3
Symbol
-
-
SHL
CST
SC
Reset
-
-
0
0
0
Access
read and write
2
1
0
AC2
AC1
AC0
0
0
0
Table 68: CCR - Clock configuration register (address 1h) bit description
Bit
Symbol
Description
7 and 6
-
Not used.
5
SHL
Select HIGH Level. This bit determines how the clock is stopped when bit CST = 1. If
SHL = 0, then the clock is stopped at LOW level, if SHL = 1 at HIGH level.
4
CST
Clock Stop. In case of an asynchronous card, bit CST defines whether the clock to the
card is stopped or not. If CST = 1, then the clock is stopped. If CST = 0, then the clock is
determined by bits AC[2:0] according to Table 69. All frequency changes are
synchronous, ensuring that no spike or unwanted pulse width occurs during changes.
3
SC
Synchronous Clock. In the event of a synchronous card, then pin CLK is the copy of the
value of bit SC. In reception mode, the data from the card is available to bit UR0 after a
read operation of register URR. In transmission mode, the data is written on the I/O line
of the card when register UTR has been written to.
2 to 0
AC[2:0]
Asynchronous card clock. When CST = 0, the clock is determined by the state of these
bits according to Table 69.
f_int is the frequency delivered by the internal oscillator clock circuitry.
For switching from ¹â„_nf_XTAL to ¹â„₂f_int and reverse, only the bit AC2 must be changed (AC1
and AC0 must remain the same). For switching from ¹â„_nf_XTAL or ¹â„₂f_int to stopped clock and
reverse, only bits CST and SHL must be changed.
When switching from ¹â„_nf_XTAL to ¹â„₂f_int and reverse, a delay can occur between the
command and the effective frequency change on pin CLK. The fastest switch is from
1_{⁄2fXTAL to} 1_{⁄2fint and reverse, the best regarding duty cycle is from} 1_{⁄8fXTAL to} 1_{⁄2fint and}
reverse. The bit CLKSW in register MSR tells the effective switch moment.
In case of f_CLK = f_XTAL, the duty cycle must be ensured by the incoming clock signal on
pin XTAL1.
Table 69: CLK value for an asynchronous card
AC2
AC1
AC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
8.10.3.6 Power control register (PCR)
This register is used for starting or stopping card sessions.
CLK
f_XTAL
1_⁄2fXTAL
1_⁄4fXTAL
1_⁄8fXTAL
1_⁄2fint
1_⁄2fint
1_⁄2fint
1_⁄2fint
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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