TDA8029 Datasheet, PDF (24/59 Pages) NXP Semiconductors – Low power single card reader

Philips Semiconductors
TDA8029
Low power single card reader
AUXR1.0
DPS
Fig 8. Dual DPTR
DPH
(83H)
DPTR1
DPTR0
DPL
(82H)
EXTERNAL
DATA
MEMORY
mhi007
8.6 Expanded data RAM addressing
The TDA8029 has internal data memory that is mapped into four separate segments.
The four segments are:
1. The lower 128 byte of RAM (addresses 00h to 7Fh), which are directly and indirectly
addressable.
2. The upper 128 byte of RAM (addresses 80h to FFh), which are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh), which are directly
addressable only.
4. The 512 byte expanded RAM (XRAM 00h to 1FFh) are indirectly accessed by move
external instructions, MOVX, if the EXTRAM bit (bit 1 of register AUXR) is cleared.
The lower 128 byte can be accessed by either direct or indirect addressing. The upper
128 byte can be accessed by indirect addressing only. The upper 128 byte occupy the
same address space as the SFRs. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 byte of data RAM or to the SFR space by the
addressing mode used in the instruction. Instructions that use direct addressing access
SFR space. For example: MOV A0h, #data accesses the SFR at location 0A0h (which is
register P2).
Instructions that use indirect addressing access the upper 128 byte of data RAM. For
example: MOV @R0, #data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
The XRAM can be accessed by indirect addressing, with EXTRAM bit (register AUXR
bit 1) cleared and MOVX instructions. This part of memory is physically located on-chip,
logically occupies the first 512 byte of external data memory.
When EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
XRAM will not affect ports P0, P3.6 (WR) and P3.7 (RD). P2 is output during external
addressing. For example: MOVX @R0, A where R0 contains 0A0h, access the EXTRAM
at address 0A0h rather than external memory. An access to external data memory
9397 750 14145
Product data sheet
Rev. 03 — 22 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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