MC68HC05BD3 Datasheet, PDF (97/112 Pages) Motorola, Inc – HCMOS microcontroller

12.6
Sync Signal Processor Timing
Table 12-5 Sync Signal Processor Timing
(V_DD=5.0Vdc ±10%, V_SS=0Vdc, temperature range=0 to 70°C)
PARAMETER
SYMBOL MINIMUM MAXIMUM UNIT
VSYNC input sync pulse
HSYNC input sync pulse
(except for composite sync input)
t_VI.SP
1
t_CYC
t_HI.SP
1
t_CYC
VTTL output sync pulse width for separate sync input
VTTL output sync pulse width for composite sync input
HTTL output sync pulse width
Free-running VTTL output sync pulse (SOUT clear)
Free-running VTTL output period (SOUT clear)
Free-running HTTL output sync pulse (SOUT clear)
Free-running HTTL output period (SOUT clear)
Inserted HTTL sync pulse (INSRT cleared)
Inserted HTTL period error (INSRT cleared)
VSYNC to VTTL delay (8pF loading)
HSYNC to HTTL delay (8pF loading)
HSYNC to VTTL delay (composite sync)
t_VO.SP
t_VO.CO
t_HO
t_FVO.SP
t_FVO
t_FHO.SP
t_FHO
t_IHI.SP
t_IHI.ER
t_VDD
t_HHD
t_HVD
same as input
input + 9.5µs input + 10µs
same as input
128
t_CYC
31488
t_CYC
4
t_CYC
41/32
t_CYC
4
t_CYC
–
1
t_CYC
30
40
ns
30
40
ns
30
40
ns
12
MC68HC05BD3
ELECTRICAL SPECIFICATIONS
TPG
MOTOROLA
12-5