MC68HC05BD3 Datasheet, PDF (63/112 Pages) Motorola, Inc – HCMOS microcontroller

Positive polarity pure horizontal sync signal
Negative polarity pure horizontal sync signal
Positive polarity composite sync signal
Negative polarity composite sync signal
Figure 8-2 Sync Signal Polarity Correction
8.1.1.2 Separate Horizontal Or Composite Sync Input
Since the input at HSYNC can be either a pure horizontal sync signal or a composite sync signal,
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different methodologies are used in polarity correction.
Unlike the polarity correction for VSYNC, both the high pulse and low pulse of the sync signal at
HSYNC are examined. If the pulse, either active high or low, is longer than a certain period (8µs
or 16 t_CYC), it will be regarded as a long pulse. If there are 8 consecutive low long pulses, the input
sync signal will be confirmed as a positive polarity sync signal, and will be inverted. If there are 8
consecutive high long pulses, it will be confirmed as a negative polarity sync signal.
The operation of this module is also continuous, and the error margin is equal to the period of the
pre-set number (default is 8) of horizontal sync pulses. At power-up or system reset, negative
polarity at input is assumed.
8.1.2 Sync Detection
The sync detector determines whether the incoming sync signal is active. Both sync high and low
pulse widths must be within the specific values to be regarded as active. HDET and VDET flags
will be set if the HSYNC and VSYNC signals are active, respectively.
MC68HC05BD3
SYNC SIGNAL PROCESSOR
TPG
MOTOROLA
8-3