MC68HC05BD3 Datasheet, PDF (67/112 Pages) Motorola, Inc – HCMOS microcontroller

8.3
Registers
There are seven registers associated with the Sync Signal Processor, these are described below.
8.3.1 Sync Signal Control & Status Register (SSCSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C VPOL HPOL VDET HDET SOUT INSRTB FOUT VSIN 0000 0000
VPOL - Vertical Sync Input Polarity
1 (set) – VSYNC input is positive polarity.
0 (clear) – VSYNC input is negative polarity.
Vertical Sync Input Polarity flag indicates the polarity of the incoming signal at the VSYNC input.
HPOL - Horizontal Sync Input Polarity
1 (set) – HSYNC input is positive polarity.
0 (clear) – HSYNC input is negative polarity.
Horizontal Sync Input Polarity flag indicates the polarity of the incoming signal at the HSYNC
input.
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VDET - Vertical Sync Signal Detect
1 (set) – An active vertical sync is detected at VSYNC input.
0 (clear) – No vertical sync signal at VSYNC input; use internal generated
Vsync for VTTL.
Vertical Sync Signal Detect flag, if set, indicates an active input vertical sync signal has been
detected. If cleared, it indicates there is no active signal, and the VTTL will output the internally
generated Vsync signal. An active vertical sync signal is defined as:
VDET = (VSYNC pulse width < 480µs or 960t_CYC)·(VSYNC period < 65.5ms or 131x10³t_CYC)
HDET - Horizontal Sync Signal Detect
1 (set) – An active horizontal sync is detected at HSYNC input.
0 (clear) – No horizontal sync signal at HSYNC input; use internal generated
Hsync for HTTL.
Horizontal Sync Signal Detect flag, if set, indicates an active input horizontal sync signal has been
detected. If cleared, it indicates there is no active signal, and the HTTL will output the internally
generated Hsync signal. An active horizontal sync signal is defined as:
HDET=(HSYNC pulse width < 8µs or 16t_CYC)·(9µs or 18t_CYC < HSYNC period < 128µs or 256t_CYC)
MC68HC05BD3
SYNC SIGNAL PROCESSOR
TPG
MOTOROLA
8-7