MC68HC05BD3 Datasheet, PDF (64/112 Pages) Motorola, Inc – HCMOS microcontroller

8.1.3 Free-running Pseudo Sync Signal Generator
If either HSYNC or VSYNC is absent, a free-running sync signal generator will be enabled. It
generates a pseudo vertical sync at 63.5Hz (1/(tcyc x 31488)) and a pseudo horizontal sync at
either 48.8 KHz (1/(t_CYC x 41)) or 62.5 KHz (1/(t_CYC x 32)), depending on the status of FOUT. This
set of free running sync signals replaces the inactive sync signals at the inputs and will be fed to
the VTTL and HTTL pins if the pins are selected for VTTL and HTTL function.
8.1.4 Sync Separation
Figure 8-3 is a block diagram of the Sync Separator which includes the duration counters for the
high and low pulses, a counter for the number of valid horizontal sync pulses, a register to hold
the number of horizontal lines per frame, a logic block for horizontal and vertical sync pulse
separation, a comparator, and a sync pulse insertion circuit.
HSYNC
load
CLK (After polarity correction)
Horizontal sync pulse counter
8
reset
count
Low pulse duration counter
Horizontal Sync Register
in
out
Comparator
equal
finish
High pulse duration counter
Sync separation logic
Sync insertion circuit
Hsync
Vsync
Figure 8-3 Sync Separator
The Low pulse duration counter examines the low pulse width of the incoming composite sync
signal. If it is within the horizontal sync pulse limit (8µs or 16 t_CYC), a horizontal sync pulse is
detected and the horizontal sync pulse counter is advanced. If the low pulse is wider than the limit,
MOTOROLA
8-4
SYNC SIGNAL PROCESSOR
TPG
MC68HC05BD3