MC68HC05BD3 Datasheet, PDF (26/112 Pages) Motorola, Inc – HCMOS microcontroller

2
DATA DIRECTION
REGISTER BIT
INTERNAL
MC68HC05
CONNECTIONS
LATCHED OUTPUT
DATA BIT
OUTPUT
I/O PIN
INPUT
REGISTER
BIT
INPUT I/O
TYPICAL PORT
DATA DIRECTION REGISTER
(a)
7
DDR 7
6
5
DDR 6 DDR 5
4
DDR 4
3
DDR 3
2
DDR 2
1
0
DDR 1 DDR 0
TYPICAL PORT REGISTER
I/O PORT LINES
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
(b)
V_DD
PORT DATA
PORT DDR
NOTE:
(1) IP = INPUT PROTECTION
(2) LATCH-UP PROTECTION NOT SHOWN
&
P
PAD
+
N
IP
INTERNAL LOGIC
MOTOROLA
2-6
(c)
Figure 2-3 Parallel Port I/O Circuitry
PIN DESCRIPTION AND I/O PORTS
TPG
MC68HC05BD3