MC68HC05BD3 Datasheet, PDF (34/112 Pages) Motorola, Inc – HCMOS microcontroller

t_VDDR
VDD
VDD THRESHOLD (TYPICALLY 1-2V)
XTAL PIN¹
4
t_oxov
INTERNAL
CLOCK²
4064 t_cyc
t_cyc
INTERNAL
ADDRESS
BUS²
3FFE
3FFF NEW PC 3FFE
3FFE
3FFF NEW PC
INTERNAL
DATA
BUS²
RESET
NEW
NEW
OP
PCL
PCH
CODE
t_RL = 1.5t_CYC
3
PCH
PCL
OP
CODE
NOTES:
1. XTAL is not meant to represent frequency. It is only used to represent time.
2. Internal clock, internal address bus, and internal data bus signals are not available externally.
3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
Figure 4-1 Power-On Reset and RESET Timing
4.1.3 Illegal Address (ILADR) Reset
The MCU monitors all opcode fetches. If an illegal address space is accessed during an opcode
fetch, an internal reset is generated. Illegal address spaces consist of all unused locations within
the memory map and the I/O registers (see Figure 3-1). Because the internal reset signal is used,
the MCU comes out of an ILADR reset in the same operating mode it was in when the opcode was
fetched.
4.1.4 Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specific amount of time by a program reset sequence.
MOTOROLA
4-2
RESETS AND INTERRUPTS
TPG
MC68HC05BD3