MC68HC05BD3 Datasheet, PDF (69/112 Pages) Motorola, Inc – HCMOS microcontroller

8.3.2 Vertical Frequency Registers (VFRS)
VFHR
VFLR
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000D
VF12 VF11 VF10 VF9 VF8 0000 0000
$000E VF7 VF6 VF5 VF4 VF3 VF2 VF1 VF0 0000 0000
This 13-bit read only register pair contains information of the vertical frame frequency. An internal
counter counts the number of internal clocks between two VSYNC pulses. The counted value will
then be transferred to this register. The data corresponds to the period of one vertical frame. This
register can be read to determine if the frame frequency is valid, and to determine the video mode.
However, the data is not valid if VDET bit is cleared.
The frame frequency is calculated by 1/(VFR±1 x 8µs) or 1/(VFR±1 x 16t_CYC).
The table below shows examples for the Vertical Frequency Register, all VFR numbers are in
hexadecimal.
Table 8-1 Vertical Frame Frequencies
VFR
Min. Freq. Max. Freq.
VFR Min. Freq. Max. Freq.
$03C0
$03C1
130.07
129.94
130.34
130.21
$0823
$0824
59.98
59.95
60.04
60.01
8
$03C2
129.80
130.07
$0825
59.92
59.98
$04E2
99.92
100.08
$09C4
49.98
50.02
$04E3
99.84
100.00
$09C5
49.96
50.00
$04E4
99.76
99.92
$09C6
49.94
49.98
$06F9
69.99
70.07
$1FFD
15.262
15.266
$06FA
69.95
70.03
$1FFE
15.260
15.264
$06FB
69.91
69.99
$1FFF
15.258
15.262
8.3.3 Line Frequency Registers (LFRs)
LFHR
LFLR
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000F HOVER
LF11 LF10 LF9 LF8 0000 0000
$0010 LF7 LF6 LF5 LF4 LF3 LF2 LF1 LF0 0000 0000
This 12-bit read only register pair contains the number of horizontal lines in each vertical frame.
An internal line counter counts the horizontal sync pulses between two vertical sync pulses. The
counted value will be transferred to this register pair. HOVER bit will be set if the incoming
horizontal sync pulses between two vertical sync pulses are more than 4096 or there is no vertical
MC68HC05BD3
SYNC SIGNAL PROCESSOR
TPG
MOTOROLA
8-9