MC68HC05BD3 Datasheet, PDF (39/112 Pages) Motorola, Inc – HCMOS microcontroller

4.2.2.2 Sync Signal Processor Interrupt
The VSYNC interrupt is generated by the Sync Signal Processor (SSP) after a vertical sync pulse
is detected as described in Section 8. The interrupt enable bit, VSIE, for the VSYNC interrupt is
located at bit 7 of Sync Signal Control register (SSCR) at $0011. The I-bit in the CCR must be
cleared in order for the VSYNC interrupt to be enabled. This interrupt will vector to the interrupt
service routine located at the address specified by the contents of $3FF8 and $3FF9. The VSYNC
interrupt latch will be cleared automatically by fetching of these vectors.
Refer to Section 8 for detailed description of Sync Signal Processor.
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4.2.2.3 M-Bus Interrupts
M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit (MIEN) of M-Bus Control register
is set, provided the interrupt mask bit of the Condition Code register is cleared. The interrupt
service routine address is specified by the contents of memory location $3FF6 and $3FF7.
M-Bus Status Register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$001A MCF MAAS MBB MAL
SRW MIF RXAK 1000 0001
MIF - M-Bus Interrupt
1 (set) – An M-Bus interrupt has occurred.
0 (clear) – An M-Bus interrupt has not occurred.
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one
of the following events occurs:
1) Completion of one byte of data transfer. It is set at the falling edge of the 9th
clock - MCF set.
2) A match of the calling address with its own specific address in slave mode -
MAAS set.
3) A loss of bus arbitration - MAL set.
This bit must be cleared by software in the interrupt routine.
MCF - Data Transfer Complete
1 (set) – A byte transfer has been completed.
0 (clear) – A byte is being transfer.
MAAS - Addressed as Slave
1 (set) – Currently addressed as a slave.
0 (clear) – Not currently addressed.
MC68HC05BD3
RESETS AND INTERRUPTS
TPG
MOTOROLA
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