MC68HC05BD3 Datasheet, PDF (46/112 Pages) Motorola, Inc – HCMOS microcontroller

The value of each PWM Data Register is continuously compared with the content of an internal
counter to determine the state of each PWM channel output pin. Double buffering is not used in
this PWM design.
M = $00
T
M = $01
32 T = 16µs
31 T
M = $0F
16 T
16 T
6
M = $1F
31 T
Pulse inserted at end of PWM cycle
depends on setting of N.
T
T=1 CPU clock period (0.5µs if CPU clock=2MHz)
M = value set in 5-bit PWM (bit3-bit7)
N = value set in 3-bit BRM (bit0-bit2)
N
PWM cycles where pulses are inserted in a 8-cycle frame
Number of inserted
pulses in a 8-cycle frame
xx1
4
1
x1x
2, 6
2
1xx
1, 3, 5, 7
4
Figure 6-1 8-Bit PWM Output Waveforms
MOTOROLA
6-2
PULSE WIDTH MODULATION
TPG
MC68HC05BD3