MC68HC05BD3 Datasheet, PDF (35/112 Pages) Motorola, Inc – HCMOS microcontroller

Note: COP time-out is prevented by periodically writing a “0” to bit 0 of address $3FF0.
If the watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode it was in when the COP time-out was generated.
The COP reset function is always enabled.
See Section 5.3 for more information on the COP watchdog timer.
4
4.2
INTERRUPTS
The MCU can be interrupted by different sources – four maskable hardware interrupt and one
non-maskable software interrupt:
• External signal on the IRQ pin
• Multi-Function Timer (MFT)
• M-Bus Interface (MBUS)
• Sync Signal Processor (SSP)
• Software Interrupt Instruction (SWI)
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
disabled. Clearing the I-bit enables interrupts.
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be
recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the
processor proceeds with interrupt processing; otherwise, the next instruction is fetched and
executed.
Table 4-1 shows the relative priority of all the possible interrupt sources.
4.2.1 Non-maskable Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is
execute regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by
the contents of memory locations $3FFC and $3FFD.
MC68HC05BD3
RESETS AND INTERRUPTS
TPG
MOTOROLA
4-3