MC68HC05BD3 Datasheet, PDF (23/112 Pages) Motorola, Inc – HCMOS microcontroller

PWM2 1
PWM1 2
42 VSYNC
41 HSYNC
2
PWM0 3
40 PWM3
RESET 4
39 PWM4
VDD 5
38 PWM5
NC 6
37 NC
VSS 7
36 PWM6
XTAL 8
35 PWM7
EXTAL 9
34 PC7/PWM15/HTTL
PB5 10
33 PC6/PWM14/VTTL
PB4 11
32 PC5/PWM13
PB3 12
31 PC4/PWM12
PB2 13
30 PC3/PWM11
PB1 14
29 PC2/PWM10
PB0 15
28 PC1/PWM9
IRQ/VPP 16
27 PC0/PWM8
PA7 17
26 PD1/SCL
PA6 18
25 PD0/SDA
PA5 19
24 PA0
PA4 20
23 PA1
PA3 21
22 PA2
Figure 2-2 Pin Assignment for 42-pin SDIP Package
2.3
INPUT/OUTPUT PORTS
In the User Mode there are 24 bidirectional I/O lines arranged as 4 I/O ports (Port A, B, C, and D).
The individual bits in these ports are programmable as either inputs or outputs under software
control by the data direction registers (DDRs). Also, if enabled by software, Port C and D will have
additional functions as PWM outputs, M-Bus I/O and Sync Signal Processor outputs.
2.3.1 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems.
The Port A data register is at $00 and the data direction register (DDR) is at $04. Reset does not
affect the data register, yet clears the data direction register, thereby returning the ports to inputs.
Writing a one to a DDR bit sets the corresponding port bit to output mode.
2.3.2 Port B
Port B is a 6-bit bidirectional port which does not share any of its pins with other subsystems. PB2
to PB5 are +10V open-drain port pins. The Port B data register is at $01 and the data direction
register (DDR) is at $05. Reset does not affect the data register, yet clears the data direction
register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding
port bit to output mode.
MC68HC05BD3
PIN DESCRIPTION AND I/O PORTS
TPG
MOTOROLA
2-3