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| MC68HC05BD3 Datasheet, PDF (62/112 Pages) Motorola, Inc – HCMOS microcontroller | |||
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VSIN FOUT
V FREQ. $0D
REGISTER $0E
VSYNC
POLARITY
CORRECTOR
MUX
HSYNC
COMPOSITE
POLARITY
CORRECTOR
V
SYNC
SEPARATOR
& INSERTION H
8
$11 SYNC SIGNAL
CONTROL REG.
INTERRUPT
CIRCUIT
VSYNC
COUNTER
SYNC
DETECTOR
VSYNC
RESHAPER
VFREE
MUX
CLK GEN.
HFREE
MUX
VDET
VTTL
R
S
SOUT
R
HTTL
HSYNC
COUNTER
SYNC
DETECTOR
HDET
INTERRUPT
LINE FREQ. $0F
REGISTERS $10
Figure 8-1 Sync Signal Processor Block Diagram
8.1.1.1 Separate Vertical Sync Input
To test the polarity of the input sync signal, the duration of the low pulse is examined. If the low
period is longer than a speciï¬c value (512µs or 1024tCYC), as in the case of positive polarity input
sync, the input sync will be inverted before output. For negative polarity input sync signal, it is
anticipated that the duration of the low pulse would be shorter than the speciï¬c value, and the input
sync signal passes through to the output without inversion.
This polarity correction is a continuous process, and the error margin is equal to the maximum
permissible sync pulse width speciï¬ed (512µs or 1024tCYC). At power-up or system reset,
negative polarity at input is assumed.
MOTOROLA
8-2
SYNC SIGNAL PROCESSOR
TPG
MC68HC05BD3
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