MC68HC05BD3 Datasheet, PDF (66/112 Pages) Motorola, Inc – HCMOS microcontroller

$0D
$0E ^{13-bit Vertical Frequency Register}
System Clock
VSYNC
HSYNC
÷16
Negative edge detector
Negative edge detector
13-bit counter
R
R
12-bit counter
$0F
$10 ^{12-bit Horizontal Line Count Register}
Figure 8-4 Sync Signal Counters Block Diagram
8
PH2
VSYNIN
Counter signal reset
Counter resets at 4 PH2 cycles
after falling edge of VSYNIN
PH2 ÷16
case1
PH2 ÷16
case2
Counter advances at the
rising edge of the clock
1. The value of the counter will be loaded into the register before it is reset.
2. The Vertical Frequency Counter is clocked by a PH2 ÷16 clock.
3. Because of the asynchronous nature between PH2 and VSYNIN, the register
will have one more count in case 2 than in case 1.
Figure 8-5 Vertical Frequency Counter Timing
MOTOROLA
8-6
SYNC SIGNAL PROCESSOR
TPG
MC68HC05BD3