MC68HC05T16 Datasheet, PDF (87/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

BR1
BR0
On-Time
(frames)
Off-Time
(frames)
0
0
24
8
0
1
48
16
1
0
96
32
1
1
192
64
HFPOL - HFLBK input polarity select
1 (set) – Horizontal flyback signal at HFLBK is active low.
0 (clear) – Horizontal flyback signal at HFLBK is active high.
HTPOL - FBKG output polarity select
1 (set) – HTONE (half tone) output pin is active low.
0 (clear) – HTONE (half tone) output pin is active high.
The HTONE output pin is shared with port pin PF3. If HTONE is disabled, HTPOL will have no
effect.
FBPOL - FBKG output polarity select
1 (set) – FBKG (fast blanking) output pin is active low.
0 (clear) – FBKG (fast blanking) output pin is active high.
RGBPOL - RGB output polarity select
1 (set) – RBG output pins are active low.
9
0 (clear) – RGB output pins are active high.
IPOL - I output polarity select
1 (set) – I (intensity) output pin is active low.
0 (clear) – I (intensity) output pin is active high.
9.5.3 Frame Control 3 and Status Register
Address bit 7 bit 6 bit 5 bit 4
$2B VFINTE MUTE1 MUTE0 VFLB
bit 3
R3CF
bit 2
R2CF
bit 1
R1CF
bit 0
R0CF
State
on reset
0000 0000
Bits 7 to 5 are control bits whereas bits 4 to 0 are status bits associated with interrupt. A status bit
is cleared by writing a 0 to that bit. Care must be taken while clearing a status bit: make sure the
MC68HC05T16
ON-SCREEN DISPLAY
TPG
MOTOROLA
9-17