MC68HC05T16 Datasheet, PDF (69/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

low cycle. A value of $7F results in a 50% duty cycle. The maximum value of $FF results in a
255/256 duty cycle. The 14-bit PWM period is 256x0.476µs=121.9µs for a CPU clock of 2.1MHz.
The 6-bit register acts as a binary rate multiplier (BRM). The value set in this register (powers of 2)
equals the number of pulses (pulse width equals to the PWM driving clock cycle) equally
distributed in a 64-PWM-cycle. A maximum value of $2x will have 32 pulses equally distributed in
64 PWM cycles (64 cycles has a period of 64x121.9µs=7.8ms).
Combining the 8-bit PWM together with the 6-bit BRM, the total average duty cycle at the output
will be (M+N/64)/256, where M is the content of the 8-bit high-order register, and N is the content
of the 6-bit low-order register. Using this mechanism, a true 14-bit resolution PWM is achieved.
Figure 8-2 shows the waveform for the 14-bit PWM channel. Note that the resulting waveform is
periodic on every 64 PWM cycles.
256 T
M = $00
T
M = $01
255 T
8
M = $7F
128 T
128 T
M = $FF
255 T
Pulse inserted at end of PWM cycle
depends on setting of N.
T
T=1 CPU clock period (0.476µs if CPU clock=2.1MHz)
M = value set in 8-bit PWM register (address $36)
N = value set in 6-bit binary rate multiplier (address $35)
N
--xxxxx1
--xxxx1x
--xxx1xx
--xx1xxx
--x1xxxx
--1xxxxx
PWM cycles where pulses are inserted in a 64-cycle frame
32
16, 48
8, 24, 40, 56
4, 12, 20, 28, 36, 44, 52, 60
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
1, 3, 5, 7, ......61, 63
Number of inserted
pulses in a 64-cycle
1
2
4
8
16
32
MC68HC05T16
Figure 8-2 14-Bit PWM Output Waveform
PULSE WIDTH MODULATOR
TPG
MOTOROLA
8-3