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MC68HC05T16 Datasheet, PDF (47/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit | |||
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contains the free-running counter value that corresponds to the most recent input capture.After a
read of the input capture register MSB ($12), the counter transfer is inhibited until the LSB ($13)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period. A read of the input
capture register LSB ($13) does not inhibit the free-running counter transfer since they occur on
opposite edges of the internal bus clock.
5.1.4 Timer Control Register (TCR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$10 ICIE OC0IE OC1IE TOVFIE
IEDG
0000 0000
5
The TCR is a read/write register containing ï¬ve control bits. Four bits control interrupts associated
with each of the four ï¬ag bits found in the Timer Status register. The other bit controls which edge
is signiï¬cant to the input capture edge detector. The Timer Control register and the free-running
counter are the only sections of the timer affected by reset.
Deï¬nition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
1 (set) â Input Capture interrupt enabled.
0 (clear) â Input Capture interrupt disabled.
OC0IE - Output Compare Interrupt Enable
1 (set) â Output Compare 0 interrupt enabled.
0 (clear) â Output Compare 0 interrupt disabled.
OC1IE - Output Compare Interrupt Enable
1 (set) â Output Compare 1 interrupt enabled.
0 (clear) â Output Compare 1 interrupt disabled.
TOVFIE - Timer Overï¬ow Interrupt Enable
1 (set) â Timer Overï¬ow interrupt enabled.
0 (clear) â Timer Overï¬ow interrupt disabled.
IEDG - Input Edge
1 (set) â TCAP is positive-going edge sensitive.
0 (clear) â TCAP is negative-going edge sensitive.
MC68HC05T16
TIMERS
TPG
MOTOROLA
5-5
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