MC68HC05T16 Datasheet, PDF (36/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

4.2.2 Software Interrupt (SWI)
The software interrupt is an executable instruction. The action of the SWI instruction is similar to
the hardware interrupts. The SWI is executed regardless of the state of the interrupt mask in the
condition code register. The service routine address is specified by the contents of memory
location $FFFC and $FFFD.
4 ^4.2.3
External Interrupt (IRQ)
The external interrupt IRQ can be software configured for “negative-edge” or “negative-edge and
level” sensitive triggering by the IRQN bit in the Multi-Function Timer register.
Multi-Function Timer Register
Address bit 7
$1C TOF
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
RTIF TOFIE RTIE IRQN WDOG RT1
bit 0
State
on reset
RT0 0000 0011
IRQN
1 (set) – Negative edge triggering for IRQ only.
0 (clear) – Level and negative edge triggering for IRQ.
When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specified by the contents of $FFF8 & $FFF9.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 4-3 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are
spaced far enough apart to be serviced. The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second configuration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Note:
The internal interrupt latch is cleared in the first part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during t_ILIL and serviced
as soon as the I bit is cleared.
MOTOROLA
4-6
RESETS AND INTERRUPTS
TPG
MC68HC05T16