MC68HC05T16 Datasheet, PDF (80/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

Background
R, G, B, or I
Char
R, G, B, or I
R, G, B, or I
FBKG
HTONE
Timing signals for 5th line (line 4)
RiBE=0, BGEN=0, FBKGCi=X RiBE=1, SHDW=0, BGEN=0, FGKGCi=X
Figure 9-4 Output Signal Timing Diagram - Without Background
9
that could have been displayed, the OSD is so designed that these remaining lines will not be
displayed. The same result applies to the complete overlap situation with different character sizes.
A row display is terminated if:
1) the part of the row display which is not overridden by other overlapping rows
has been completed, or
2) it completely overlaps a row or rows with higher priority, or
3) the part of the row display which does not overlap vertical retrace period has
been completed. (This applies to rows immediately before vertical retrace)
Note that the judgement of overlap is totally based on the vertical position of rows, it has nothing
to do with character size of rows. RiCF bit of Frame Control 3 and Status register will also be set
when a row display is terminated.
MOTOROLA
9-10
ON-SCREEN DISPLAY
TPG
MC68HC05T16