MC68HC05T16 Datasheet, PDF (84/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

Table 9-2 Number of Visible Characters Per Row
dot matrix
char size
1H x 1V
2H x 2V
3H x 3V
4H x 4V
16 x 16
24
12
8
6
12 x 16
32
16
11
8
9.5.1 Frame Control 1 and Row Count Register
Address bit 7 bit 6
$1D PLLEN DSCAN
bit 5
FADE
bit 4 bit 3 bit 2 bit 1 bit 0
ON/OFF CDRC3 CDRC2 CDRC1 CDRC0
State
on reset
0000 0000
Bits 7 to 4 are control bits and, bits 3 to 0 are status bits.
PLLEN - PLL enable bit
1 (set) – PLL enabled for OSD clock source.
0 (clear) – PLL disabled.
DSCAN - Double/Single scan mode select
9
1 (set) – Double scan mode.
0 (clear) – Single scan mode.
DSCAN (double scan) bit is for the control of OSD logic so that the OSD can accommodate
non-interlaced scan TV system by adjusting dot matrix scan output. Users have to determine if the
target TV broadcast system is a double scan system. If DSCAN is set, all horizontal lines in the
character dot matrix will be displayed twice in the same frame. The other feature associated with
horizontal lines that will also be doubled is the RiVP6-RiVP0 field of Row Vertical Position
Registers.
FADE - Display fade enable
1 (set) – Display fade function enabled.
0 (clear) – Display fade function disabled.
The FADE bit controls the sequence of frame display appearance and disappearance. When
FADE bit is set, frame display will gradually appear (fade in) if ON/OFF is set, and gradually
disappear (fade out) if ON/OFF is clear. If FADE bit is clear, OSD display will be turned on or off
instantly.
MOTOROLA
9-14
ON-SCREEN DISPLAY
TPG
MC68HC05T16