MC68HC05T16 Datasheet, PDF (79/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

Figure 9-4 and Figure 9-5 illustrate the timing signals of R, G, B, I, FBKG, and HTONE as a
function of control bits BGEN, RiBE, and FBKGCi, using the 5th line (line 4) of a 12x16 dot matrix
as an example. All output signals assume positive polarity.
Figure 9-4 illustrates the timing of output signals for characters with and without bordering effect.
Figure 9-5 illustrates the output signal timing for characters with background enabled, yet with
opposite FBKGCi bit setting. Note that both RiBE and FBKGCi are row features. Hence, the two
adjacent dot matrices in both figures are drawn for demonstration purposes only, they do not imply
that users can configure OSD display in such a manner that one character has FBKGCi bit set and
the next character in the same row has FBKGCi bit cleared. Note that ‘HTONE’ has exactly the
same waveform as ‘Background R,G,B, or I’. Output signal timing diagram similar to Figure 9-5 for
the case where character bordering is enabled can be derived in very similar fashion. The only
difference is that ‘FBKG’ will be on and ‘HTONE’ will be off where a bordering dot exists. Other
output signal timings remain the same.
RiVP6 to RiVP0 - Row i Vertical Position
For single scan mode: Vertical position = RiVPx setting x 4
For double scan mode: Vertical position = RiVPx setting x 4 x 2
Each RiVP6-RiVP0 step shifts the vertical position of row i by 4 horizontal display lines. For single
scan mode, the shift is (RiVP6-RiVP0)x4 horizontal lines. For double scan mode, the shift is
((RiVP6-RiVP0)x4) x 2 horizontal lines. The calculation of shift is a function of scan mode, not
character size selection. Hence, care should be taken when choosing vertical position for a
particular row that locates after a row which has character size other than the basic 12x16 or
16x16 setting. For example, assuming single scan mode, if row X has 4Hx4V character size and
vertical position of $40 while row Y has basic character size of 1Hx1V and vertical position of $48,
then row X will be displayed from the 256th (64x4) line to the 287th line, which covers only the first
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32 lines of the supposed 64-line row X display, and row Y will be displayed from the 288th (72x4)
line to 303th line without any missing lines.
The reference point of shift is the leading edge of vertical flyback input signal, VFLBK. As a result
of this vertical start position granularity, there are a total of 262.5/4 row positions in a full
screen.
In Figure 9-6(a), row (i+1) and row i partially overlaps. Since the vertical position of row (i+1) is
lower than row i, row (i+1) will be partially covered by row i. New symbols may be generated when
rows are partially overlapped.
In Figure 9-6(b), row (j+1) is completely covered by row j. As result, only row j is visible.
Note that in cases where the character size of the blocked row is bigger than that of the blocking
row, once the blocked row has been blocked, it will never be displayed again even after the
blocking row display has been terminated. For example, assume the character size of row (i+1) is
4Hx4V and that of row i is 1Hx1V, and the difference in vertical position between them is 4
horizontal lines only. After the first four lines of row (i+1) have been displayed, row i display will
commence and continue for the next sixteen lines, blocking off row (i+1) display for these sixteen
lines. After row i display has been terminated, there are still (64-4-16)=44 lines of row (i+1) display
MC68HC05T16
ON-SCREEN DISPLAY
TPG
MOTOROLA
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