MC68HC05T16 Datasheet, PDF (60/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

6.3.1 M-Bus Address Register (MADR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$37 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
0000 0000
ADR1-ADR7 are the slave address bits of the M-Bus module.
6.3.2 M-Bus Clock Register (MCKR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$38
MBC4 MBC3 MBC2 MBC1 MBC0 0000 0000
6
MBC0-MBC4 are used for clock rate selection. The serial bit clock frequency is equal to the CPU
clock divided by the divider shown in Table 6-1.
Table 6-1 M-Bus Prescaler
MBC4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MBC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MBC2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MBC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MBC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIVIDER
22
24
28
34
44
48
56
68
88
96
112
136
176
192
224
272
MBC4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MBC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MBC2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MBC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MBC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIVIDER
352
384
448
544
704
768
896
1088
1408
1536
1792
2176
2816
3072
3584
4352
For a 4.2MHz external crystal operation (2.1MHz internal operating frequency), the serial bit clock
frequency of M-Bus ranges from 483Hz to 95,455Hz.
MOTOROLA
6-6
M-BUS SERIAL INTERFACE
TPG
MC68HC05T16