MC68HC05T16 Datasheet, PDF (35/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

Table 4-2 Reset/Interrupt Vector Addresses
Register
Flag Name
Interrupt
CPU Interrupt
Vector Address
–
–
Reset
RESET
$FFFE-$FFFF
–
–
Software
SWI
$FFFC-$FFFD
VFLB
Vertical Flyback
OSD Status
R3CF/R2CF/
R1CF/R0CF
OSD Row Completion
OSD
$FFFA-$FFFB
–
–
ICF
External Interrupt
Input Capture
IRQ
$FFF8-$FFF9
4
Timer Status
OC0F/OC1F
Output Compare
TIMER
$FFF6-$FFF7
TOF
Timer Overflow
ALOST
Arbitration Loss
M-Bus Status
SELTED
Addressed as Slave
M-BUS
$FFF4-$FFF5
MCF
Transfer Complete
PAC Control
PAOF
Pulse Accumulator Overflow
PAC
$FFF2-$FFF3
Multi-Function
RTIF
Timer
TOF
Real Time Interrupt
Timer Overflow
MFT
$FFF0-$FFF1
4.2.1 Hardware Controlled Sequences
The following three functions are not strictly interrupts, however, they are tied very closely to the
interrupts. These functions are RESET, STOP, WAIT.
1) RESET
2) STOP
3) WAIT
The RESET input pin causes the program to go to its starting
address. This address is specified by the contents of memory
locations $FFFE and $FFFF. The interrupt mask of the condition
code register is also set. Most parts of the MCU is configured to
some known state as described in Table 4-1.
The STOP instruction causes the oscillator to be turned off and
the processor “sleeps” until an external interrupt (IRQ) or RESET
occurs. See section 12 on Low Power Modes.
The WAIT instruction causes all processor clocks to stop, but
leaves the Timer and PAC clocks running. This “rest” state of the
processor can be exited by RESET, an external interrupt (IRQ),
or any of the interrupts described above. There are no special
wait vectors for these individual interrupts. See section 12 on
Low Power Modes.
MC68HC05T16
RESETS AND INTERRUPTS
TPG
MOTOROLA
4-5