MC68HC05T16 Datasheet, PDF (27/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

3
3
MEMORY AND REGISTERS
This section describes the organization of the on-chip memory.
3.1
Memory Map
The CPU can address 64K-bytes of memory space. The ROM portion of memory holds the
program instructions, fixed data, user-defined vectors, and interrupt service routines. The RAM
portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can
access their locations in the same way that it accesses all other memory locations. Figure 3-1
shows the Memory Map for the MC68HC05T16/MC68HC705T16.
3.2
Input/Output Section
The first 64 addresses of memory space, $0000-$003F, are the I/O section. These are the
addresses of the I/O control registers, status registers, and data registers. Table 3-1 shows these
registers and their respective bits.
3.3
RAM
The 320 addresses from $0050-$018F are RAM locations. The CPU uses the 64 RAM addresses,
$00C0-$00FF, as the stack. Before processing an interrupt, the CPU uses five bytes of the stack
to save the contents of the CPU registers. During a subroutine call, the CPU uses two bytes of the
stack to store the return address. The stack pointer decrements during pushes and increments
during pulls.
Note:
Be careful when using nested subroutines or multiple interrupt levels. The CPU may
overwrite data in the RAM during a subroutine or during the interrupt stacking
operation. Once the stack pointer passes $00C0, it wraps round back to $00FF.
MC68HC05T16
MEMORY AND REGISTERS
TPG
MOTOROLA
3-1