MC68HC05T16 Datasheet, PDF (65/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

7
PULSE ACCUMULATOR
The Pulse Accumulator is an 8-bit counter that can operate in either of two modes; event counting
mode and the gated time accumulation mode. The operating mode is selected by a control bit in
the Pulse Accumulator Control register.
In the event counting mode, the 8-bit counter is clocked by the signal on the PACIN pin. The
maximum clocking rate for the external counting mode is E (CPU) clock divided by two.
In the gated time accumulation mode, the 8-bit counter is driven by E clock divided by 64. The
counter will increment when PACIN pin is high and halt when PACIN is low.
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7.1
Pulse Accumulator Registers
Two registers are associated with the Pulse Accumulator; they are described below.
7.1.1 PAC Control and Status Register (PACTL)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0E PAOF PAEN PAMOD PAIE
0000 0000
Register bit definitions:
PAOF - PAC Overflow Interrupt Flag Bit.
1 (set) – A PAC overflow from $FF to $00 has occurred.
0 (clear) – No PAC overflow has occurred.
It is set when the count in the pulse accumulator rolls over from $FF to $00. PAOF is cleared by
writing a “0” to the bit. An interrupt to the CPU is generated if the PAIE bit is set.
MC68HC05T16
PULSE ACCUMULATOR
TPG
MOTOROLA
7-1