MC68HC05T16 Datasheet, PDF (62/128 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

6.3.4 M-Bus Status Register (MSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$3A MCF SELTED BBSY ALOST
SRW MIF RXACKB 1000 0001
The MIF and ALOST bits are software clearable; while the other bits are read only.
MCF - Data Transfer Complete Flag
1 (set) – A byte transfer has been completed.
0 (clear) – A byte is being transfer.
When MCF is set, the MIF (M-bus interrupt) bit is also set. An M-bus interrupt is generated if the
MIEN bit is set.
6
SELTED - Addressed as Slave Bit
1 (set) – Currently addressed as a slave.
0 (clear) – Not currently addressed.
This SELTED bit is set when its own specific address (M-Bus Address register) matches the
calling address. When SELTED is set, the MIF (M-bus interrupt) bit is also set. An interrupt is
generated if the MIEN bit is set. Then CPU needs to check the SRW bit and set its XMT bit
accordingly. Writing to the M-Bus Control register clears this bit.
BBSY - Bus Busy Bit
1 (set) – M-Bus busy.
0 (clear) – M-Bus idle.
This bit indicates the status of the bus. When a START signal is detected, BBSY is set. If a STOP
signal is detected, it is cleared.
ALOST - Arbitration Lost Flag
1 (set) – Lost arbitration in master mode.
0 (clear) – No arbitration lost.
This arbitration lost flag is set when the M-bus master loses arbitration during a master
transmission mode. When ALOST is set, the MIF (M-bus interrupt) bit is also set. This bit must be
cleared by software.
MOTOROLA
6-8
M-BUS SERIAL INTERFACE
TPG
MC68HC05T16