MC68HC12 Datasheet, PDF (400/478 Pages) Motorola, Inc – The MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit

Development Support
Figure 20-2 shows the host receiving a logic one from the target
MC68HC912DT128A MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The
host holds the BKGD pin low long enough for the target to recognize it
(at least two target B cycles). The host must release the low drive before
the target MCU drives a brief active-high speed-up pulse seven cycles
after the perceived start of the bit time. The host should sample the bit
level about ten cycles after it started the bit time.
BDMCLK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
TARGET MCU
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
EARLIEST
START OF
NEXT BIT
HC12A4 BDM TARGET TO HOST TIM 0
Figure 20-3. BDM Target to Host Serial Bit Timing (Logic 0)
Technical Data
400
Development Support
MC68HC912DT128A — Rev 4.0
MOTOROLA