MC68HC12 Datasheet, PDF (314/478 Pages) Motorola, Inc – The MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit

Inter IC Bus
RSTA — Repeat Start
Writing a 1 to this bit will generate a repeated START condition on the
bus, provided it is the current bus master. This bit will always be read
as a low. Attempting a repeated start at the wrong time, if the bus is
owned by another master, will result in loss of arbitration.
1 = Generate repeat start cycle
IBSWAI — IIC Stop in WAIT mode
0 = IIC module operates normally
1 = Halt clock generation of IIC module in WAIT mode
IBSR — IIC Bus Status Register
$00E3
Bit 7
6
5
4
3
2
1
Bit 0
TCF
IAAS
IBB
IBAL
0
SRW
IBIF
RXAK
RESET:
1
0
0
0
0
0
0
0
This status register is read-only with exception of bit 1 (IBIF) and bit 4
(IBAL), which are software clearable
TCF — Data transferring bit
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the 9th clock of a byte transfer.
0 = Transfer in progress
1 = Transfer complete
IAAS — Addressed as a slave bit
When its own specific address (IIC Bus Address Register) is matched
with the calling address, this bit is set. The CPU is interrupted
provided the IBIE is set. Then the CPU needs to check the SRW bit
and set its Tx/Rx mode accordingly. Writing to the IIC Bus Control
Register clears this bit.
0 = Not addressed
1 = Addressed as a slave
IBB — IIC Bus busy bit
This bit indicates the status of the bus. When a START signal is
detected, the IBB is set. If a STOP signal is detected, it is cleared.
0 = Bus is idle
1 = Bus is busy
Technical Data
314
Inter IC Bus
MC68HC912DT128A — Rev 4.0
MOTOROLA