MC68HC12 Datasheet, PDF (284/478 Pages) Motorola, Inc – The MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit

Multiple Serial Interface
In the long mode, the SCI circuitry does not begin counting ones in the
search for the idle line condition until a stop bit is received. Therefore,
the last byte’s stop bit and preceding “1” bits do not affect how quickly
an idle line condition can be detected.
PE — Parity Enable
0 = Parity is disabled.
1 = Parity is enabled.
PT — Parity Type
If parity is enabled, this bit determines even or odd parity for both the
receiver and the transmitter.
0 = Even parity is selected. An even number of ones in the data
character causes the parity bit to be zero and an odd number
of ones causes the parity bit to be one.
1 = Odd parity is selected. An odd number of ones in the data
character causes the parity bit to be zero and an even number
of ones causes the parity bit to be one.
SC0CR2/SC1CR2 — SCI Control Register 2
$00C3/$00CB
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt will be requested whenever the TDRE status flag
is set.
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt will be requested whenever the TC status flag is
set.
Technical Data
284
Multiple Serial Interface
MC68HC912DT128A — Rev 4.0
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