MC68HC12 Datasheet, PDF (260/478 Pages) Motorola, Inc – The MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit

Enhanced Capture Timer
TC4 — Timer Input Capture/Output Compare Register 4
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC5 — Timer Input Capture/Output Compare Register 5
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC6 — Timer Input Capture/Output Compare Register 6
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
$0098–$0099
1
Bit 0
9
Bit 8
1
Bit 0
$009A–$009B
1
Bit 0
9
Bit 8
1
Bit 0
$009C–$009D
1
Bit 0
9
Bit 8
1
Bit 0
TC7 — Timer Input Capture/Output Compare Register 7
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
$009E–$009F
1
Bit 0
9
Bit 8
1
Bit 0
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when a
defined transition is sensed by the corresponding input capture edge
detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All timer
input capture/output compare registers are reset to $0000.
PACTL — 16-Bit Pulse Accumulator A Control Register
BIT 7
6
5
4
0
PAEN PAMOD PEDGE
RESET:
0
0
0
0
3
CLK1
0
2
CLK0
0
1
PAOVI
0
BIT 0
PAI
0
$00A0
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit
pulse accumulators PAC3 and PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin
with IC7.
Read: any time
Write: any time
Technical Data
260
Enhanced Capture Timer
MC68HC912DT128A — Rev 4.0
MOTOROLA