M68HC128 Datasheet, PDF (333/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
Instruction Tagging
18.4.2.6 Breakpoint Data Register Low Byte
Address: $0025
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Power on reset: 0
0
0
0
0
0
0
0
Figure 18-15. Breakpoint Data Register Low (BRKDL)
NOTE:
These bits are compared to the least significant byte of the data bus in full
breakpoint mode or the least significant byte of the address bus in dual address
modes. BKEN1, BKEN0, BKDBE, BK1ALE, and BKMBL control how this byte is
used in the breakpoint comparison.
After a power-on reset, registers BRKAH, BRKAL, BRKDH, and BRKDL are
cleared but these registers are not affected by normal resets.
18.5 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real
time or from trace history that was captured by a logic analyzer. However, the
reconstructed queue cannot be used to stop the CPU at a specific instruction,
because execution has already begun by the time an operation is visible outside
the MCU. A separate instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for tagging.
Tagging information is latched on the falling edge of ECLK along with program
information as it is fetched. Tagging is allowed in all modes. Tagging is disabled
when BDM becomes active and BDM serial commands cannot be processed while
tagging is active.
TAGHI is a shared function of the BKGD pin.
TAGLO is a shared function of the PE3/LSTRB pin, a multiplexed I/O pin. For 1/4
cycle before and after the rising edge of the E clock, this pin is the LSTRB driven
output.
TAGLO and TAGHI inputs are captured at the falling edge of the E clock. A logic 0
on TAGHI and/or TAGLO marks (tags) the instruction on the high and/or low byte
of the program word that was on the data bus at the same falling edge of the E
clock.
Table 18-10 shows the functions of the two tagging pins. The pins operate
independently; the state of one pin does not affect the function of the other. The
presence of logic level 0 on either pin at the fall of ECLK performs the indicated
function. Tagging is allowed in all modes. Tagging is disabled when BDM becomes
active and BDM serial commands are not processed while tagging is active.
M68HC12B Family — Rev. 9.0
MOTOROLA
Development Support
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
333